Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits

This paper presents the fabrication and electrical characterization of high aspect-ratio (AR) sub-micron diameter through silicon vias (TSVs) for densely interconnected three-dimensional (3D) stacked integrated circuits (ICs). The fabricated TSV technology features an AR of 16:1 with 680 nm diameter copper (Cu) core and 920 nm overall diameter. To address the challenges in scaling TSVs, scallop-free low roughness nano-Bosch silicon etching and direct Cu electroplating on a titanium-nitride (TiN) diffusion barrier layer have been developed as key enabling modules. The electrical resistance of the sub-micron TSVs is measured to be on average 1.2 Ω, and the Cu resistivity is extracted to be approximately 2.95 μΩ cm. Furthermore, the maximum achievable current-carrying capacity (CCC) of the scaled TSVs is characterized to be approximately 360 μA for the 680 nm Cu core.